Spirent and Synopsys Collaborate to Accelerate the Silicon Development Time-to-Market
New networking SoC test solution bridges the gap between pre-silicon and post-silicon verification
CALABASAS, CA. – September 1, 2021–(LSE:SPT), the leading provider of test, assurance and analytics solutions for next-generation devices and networks, today announced a collaboration with Synopsys to deliver a networking system-on-chip (SoC) verification solution to bridge the gap between pre- and post-silicon verification. The Spirent Chip Design Verification Solution speeds up the entire silicon development lifecycle and delivers significant cost savings by identifying and addressing issues in the IC design phase and before manufacturing starts. Combining network testing technology from the leading Ethernet test company with an industry-leading emulation system provides more accurate and faster verification for Ethernet SoCs.
Spirent’s TestCenter platform is a networking traffic generator, providing automated, scalable and accurate Ethernet test patterns, which are a necessity for networking ASIC and SoC verification engineers. It is tightly integrated with Synopsys ZeBu® Server, a leading emulation system, enabling pre-silicon SoC validation from 1G to 800G. The integration between the traffic generator and ZeBu Server is time-synced, which allows accurate and realistic Layer 2-3 traffic generation and real-time results analysis.
“Given our breadth of test solutions, we value partnering with EDA vendors to bridge the gap between pre- and post-silicon validation of next-generation networking products,” said Malathi Malla, Head of Go to Market Strategy and Operations of Cloud & IP at Spirent Communications. “Together with Synopsys, we are providing access to the latest Chip Design Verification solution that allows our customers to identify critical problems early in the design lifecycle and accelerate their time to market. Customers are able to simplify test complexity, reduce development time and assure that new products perform as expected.”
Leveraging the Spirent Chip Design Verification Solution in all phases of the chipset ecosystem provides:
Improved operational efficiency and flexibility using virtualized testbeds
Reduced complexity of network testing through actionable analytics and intuitive reporting
Automation and reusability of test configurations between pre- and post-silicon teams
“By collaborating with leaders in test solutions, we enable networking companies to optimize time-to-revenue for new networking SoCs,” said Susheel Tadikonda, vice president of Solutions Engineering in the Synopsys Verification Group. “We’re excited to collaborate with Spirent to deliver innovative and comprehensive virtual test solutions based on the high performance of ZeBu emulation systems and the Spirent TestCenter platform to perform pre- to post-silicon validation.”
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